Embodiments of the inventive concept relate to a semiconductor logic circuit, and more particularly, to a clock-delayed domino logic circuit robust to on-chip variation (OCV) and devices including the same.
With the increasing demand on a high-performance mobile central processing unit (CPU), the importance of a digital circuit that can operate at high speed in the CPU is increasing.
Domino logic is used for the digital circuit. The domino logic is a complementary metal oxide semiconductor (CMOS)-based evolution of dynamic logic techniques based on either P-channel MOS (PMOS) or N-channel MOS (NMOS) transistors.
The domino logic includes stages connected in cascade and a buffer between the stages to delay a clock signal. The domino logic is also referred to as clock-delayed domino logic. For the reliable operation of the clock-delayed domino logic, the evaluation or pull-down of a logic network of the clock-delayed domino logic may be terminated while the buffer is delaying the clock signal.